1. Field
This disclosure relates generally to circuits, and more specifically, to a phase locked loop circuit having a voltage controlled oscillator with improved bandwidth.
2. Related Art
A phase locked loop (PLL) circuit is used to generate a clock signal. The PLL circuit generally includes a voltage controlled oscillator (VCO) to generate the clock signal in response to a control voltage. LC (inductor-capacitor) oscillators are used in some VCO circuits to provide high quality clock sources. However, an integrated circuit having multiple PLL circuits with LC oscillators may experience injection locking problems when mutual coupling occurs between the PLL circuits. The injection locking problems can result in poor jitter performance at the PLL output.
To overcome the injection locking problem, a combination of LC oscillators and ring oscillators may be used to prevent two neighboring LC oscillators from running in the same frequency range. Ring oscillators are then used to fill in any missing gaps in the operational frequencies. However, ring oscillators may suffer from several limitations in high frequency applications, such as for example, microwave frequencies. For example, the available maximum frequency of a ring oscillator is determined by a gain-bandwidth product of its gain stages. In order to operate at higher frequencies, the gain stages of the ring oscillators with sufficiently high speed and high gain are desirable. Therefore, higher transconductance, and in turn higher gain with higher power consumption is usually expected. Also, the VCO tuning range has to be sufficiently wide to cover frequency variations over supply voltage, temperature, and silicon process variations. In addition, the tuning circuits may cause extra parasitic loading that limits the maximum frequency. Further, the VCO conversion gain must be optimized with respect to the VCO frequency tuning range, adding complexity to the PLL design.
Therefore, what is needed is a PLL circuit that solves the above problems.